Merge pull request #316 from antonblanchard/verilator-fix
authorPaul Mackerras <paulus@ozlabs.org>
Sat, 14 Aug 2021 00:18:42 +0000 (10:18 +1000)
committerGitHub <noreply@github.com>
Sat, 14 Aug 2021 00:18:42 +0000 (10:18 +1000)
commit8cdb00652b1693d1c4fefd20c9de3d2900cc0ecc
treea6d52a00b96623cefd035be57504f65f98b7e203
parent71af8016da0c8183ddc63b1ea77ed87f436b3591
parentbc0f7cf23634e4336d745b92b45f22914a57bef6
Merge pull request #316 from antonblanchard/verilator-fix

Rename 'do' signal to avoid verilator System Verilog warning