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(parent: 65a4d55) | patch
radeonsi: implement TC L2 write-back (flush) without cache invalidation
authorMarek Olšák <marek.olsak@amd.com>
Mon, 10 Oct 2016 16:49:22 +0000 (18:49 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 12 Oct 2016 16:29:40 +0000 (18:29 +0200)
commit8cdce30cc20983dcb971dd906a9a9007e282081d
treed807f6a1400a42c99add320d75eae3aac988e2e5tree
parent65a4d55a9ff12b44655803da10112d3b1b42ce13commit | diff
radeonsi: implement TC L2 write-back (flush) without cache invalidation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeonsi/si_pipe.h diff | blob | history
src/gallium/drivers/radeonsi/si_state_draw.c diff | blob | history