intel: Fix broxton 2x6 way size computation
authorAnuj Phogat <anuj.phogat@gmail.com>
Tue, 6 Jun 2017 23:14:19 +0000 (16:14 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Wed, 7 Jun 2017 04:30:51 +0000 (21:30 -0700)
commit8d02916e0c083f57bc7dfd886333f099763bd998
tree7d248a5dfbb952f80ab187504454f5fc396d3d82
parent86eff151b1252fca5942390bace106b82caa9725
intel: Fix broxton 2x6 way size computation

This patch is undoing the changes to way size computation
in broxton 2x6, made by below commit:

Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138
Author:     Anuj Phogat <anuj.phogat@gmail.com>
i965: Simplify l3 way size computations

By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
src/intel/common/gen_l3_config.c