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(parent: 1ad0b01) | patch
add ASCII dump of BRAM read/write data and add one-cycle delay on read
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 22:04:06 +0000 (22:04 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 22:04:06 +0000 (22:04 +0000)
commit8d234cae74f1a46d190a7febc248754e943a5fbb
treee1f861bfcd260368a85a4b54a7556caaaca4405atree
parent1ad0b014fd7b5f24498533876fd0061ecacd8c52commit | diff
add ASCII dump of BRAM read/write data and add one-cycle delay on read
the BRAM outputs its data one cycle late from the read-enable (bram_re)
verilator/microwatt-verilator.cpp diff | blob | history