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(parent: b7003d0) | patch
add PLL reset stability time option (defaults to 18 bits)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 13:40:40 +0000 (13:40 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 27 Feb 2022 13:40:40 +0000 (13:40 +0000)
commit8d2423d2003180faf7beeb7d9216ea58f21e822b
tree531b90ddc777df19b2dd67e5bd6164f8a2a4550ctree
parentb7003d089e1147469a807256dc4721283fce3a37commit | diff
add PLL reset stability time option (defaults to 18 bits)
to fpga/top-generic.vhdl
fpga/top-generic.vhdl diff | blob | history