mem-ruby: Fixing MESI Three Level
authorPouya Fotouhi <pfotouhi@ucdavis.edu>
Sat, 19 Jan 2019 23:41:37 +0000 (15:41 -0800)
committerPouya Fotouhi <pfotouhi@ucdavis.edu>
Tue, 12 Feb 2019 05:51:07 +0000 (05:51 +0000)
commit8d7933293f030f180db5effc01865286ba682ca3
tree9e4d3bd906795c7972c9f974c5fff3e87704f073
parent502af7c0f58e53105c78cc0cea39404904a09214
mem-ruby: Fixing MESI Three Level

Adding back some changes done in patch 676ae57827.
Transient state IS_I, STALE_DATA, Data_Stale event are necessary.

Issue: (cacheline A, initial state for P0 and P1 is I)
|   P0   |   P1   |
|GETX (A)|        |
|        |GETS (A)|
|Inv_All |        |
P1 never sends the ACK - deadlock
It should ACK, later upon data use it as stale data, and got to I.

Solution:
P1(A):
GETS:    I->IS
Inv_All: IS->IS_I, Send ACK
Data:    IS_I->I, STALE_DATA to L0

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f
Reviewed-on: https://gem5-review.googlesource.com/c/15715
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
src/mem/protocol/MESI_Three_Level-L0cache.sm
src/mem/protocol/MESI_Three_Level-L1cache.sm
src/mem/protocol/MESI_Three_Level-msg.sm