projects / gem5.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: cda354b) | patch
Turn the instruction tracing code into pluggable sim objects.
authorGabe Black <gblack@eecs.umich.edu>
Sun, 29 Jul 2007 03:30:43 +0000 (20:30 -0700)
committerGabe Black <gblack@eecs.umich.edu>
Sun, 29 Jul 2007 03:30:43 +0000 (20:30 -0700)
commit8dd7700482b8ad7fa5e96469b23f0c917f5e3599
treec1e9e7e835a12992eda9f9ee90e4f984816ed059tree
parentcda354b07035f73a3b220f89014721300d36a815commit | diff
Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.

--HG--
extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
23 files changed:
src/cpu/BaseCPU.py diff | blob | history
src/cpu/ExeTracer.py [new file with mode: 0644] blob
src/cpu/IntelTrace.py [new file with mode: 0644] blob
src/cpu/LegionTrace.py [new file with mode: 0644] blob
src/cpu/NativeTrace.py [new file with mode: 0644] blob
src/cpu/SConscript diff | blob | history
src/cpu/base.cc diff | blob | history
src/cpu/base.hh diff | blob | history
src/cpu/exetrace.cc diff | blob | history
src/cpu/exetrace.hh diff | blob | history
src/cpu/inteltrace.cc [new file with mode: 0644] blob
src/cpu/inteltrace.hh [new file with mode: 0644] blob
src/cpu/legiontrace.cc [new file with mode: 0644] blob
src/cpu/legiontrace.hh [new file with mode: 0644] blob
src/cpu/nativetrace.cc [new file with mode: 0644] blob
src/cpu/nativetrace.hh [new file with mode: 0644] blob
src/cpu/o3/fetch_impl.hh diff | blob | history
src/cpu/simple/atomic.cc diff | blob | history
src/cpu/simple/base.cc diff | blob | history
src/cpu/simple/timing.cc diff | blob | history
src/sim/InstTracer.py [new file with mode: 0644] blob
src/sim/SConscript diff | blob | history
src/sim/insttracer.hh [new file with mode: 0644] blob