git.libre-soc.org Git - microwatt.git/commit

author	Benjamin Herrenschmidt <benh@kernel.crashing.org>
	Wed, 23 Oct 2019 01:08:55 +0000 (12:08 +1100)
committer	Benjamin Herrenschmidt <benh@kernel.crashing.org>
	Wed, 30 Oct 2019 02:18:58 +0000 (13:18 +1100)
commit	8e0389b9736c60572e13ef5eeb50d3a775c3ffc6
tree	5eeb09c80251f3a239b3b1c49a3c4f0eda84e312	tree
parent	9a63c098a5471e40ca0364a867d30204f0288bc4	commit \| diff

ram: Rework main RAM interface

This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

24 files changed:

Makefile		diff \| blob \| history
README.md		diff \| blob \| history
core_tb.vhdl		diff \| blob \| history
dcache_tb.vhdl		diff \| blob \| history
dmi_dtm_tb.vhdl		diff \| blob \| history
fpga/main_bram.vhdl	[new file with mode: 0644]	blob
fpga/mw_soc_memory.vhdl	[deleted file]	blob \| history
icache_tb.vhdl		diff \| blob \| history
microwatt.core		diff \| blob \| history
scripts/run_test.sh		diff \| blob \| history
scripts/test_micropython.py		diff \| blob \| history
scripts/test_micropython_long.py		diff \| blob \| history
sim_bram.vhdl	[new file with mode: 0644]	blob
sim_bram_helpers.vhdl	[new file with mode: 0644]	blob
sim_bram_helpers_c.c	[new file with mode: 0644]	blob
simple_ram_behavioural.vhdl	[deleted file]	blob \| history
simple_ram_behavioural_helpers.vhdl	[deleted file]	blob \| history
simple_ram_behavioural_helpers_c.c	[deleted file]	blob \| history
simple_ram_behavioural_tb.bin	[deleted file]	blob \| history
simple_ram_behavioural_tb.vhdl	[deleted file]	blob \| history
soc.vhdl		diff \| blob \| history
wishbone_bram_tb.bin	[new file with mode: 0644]	blob
wishbone_bram_tb.vhdl	[new file with mode: 0644]	blob
wishbone_bram_wrapper.vhdl	[new file with mode: 0644]	blob

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