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(parent: 63cc07c) | patch
back.rtlil: only translate switch tests once.
authorwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 07:17:33 +0000 (07:17 +0000)
committerwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 07:17:52 +0000 (07:17 +0000)
commit8e2690af264ea29d97dd81a8bbb7db37aa8d6d97
tree57d665fd639ad32fa6f6ab20ea6e5bc96fd863d0tree
parent63cc07cf700153e323c8cd5052ad742d505510ffcommit | diff
back.rtlil: only translate switch tests once.

This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
nmigen/back/rtlil.py diff | blob | history