wire out signals needed for verilator simulation
authorTobias Platen <tplaten@posteo.de>
Sat, 2 Apr 2022 19:13:09 +0000 (21:13 +0200)
committerTobias Platen <tplaten@posteo.de>
Sat, 2 Apr 2022 19:13:09 +0000 (21:13 +0200)
commit8e2bd0c4ca753ba4331b352af16ad7bac9b40420
treec5b33e6fae0acbf67ed16a48f4bb6fd9c6266443
parent231963af4e07d311d32d420a3e48708052c6aca3
wire out signals needed for verilator simulation
fpga/top-generic.vhdl