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(parent: 08eb082) | patch
write_verilog: emit intermediate wire for constant values in sensitivity list
authorN. Engelhardt <nak@symbioticeda.com>
Mon, 28 Sep 2020 16:11:18 +0000 (18:11 +0200)
committerN. Engelhardt <nak@symbioticeda.com>
Mon, 28 Sep 2020 16:11:18 +0000 (18:11 +0200)
commit8f1d53e66f62ba140e4cd0d85a3ea69089825c56
tree6f846582c061e7f305271aef2d342c09ed9aa1c7tree
parent08eb0821c9c62ef21e054b6a53a980019bbfa6cacommit | diff
write_verilog: emit intermediate wire for constant values in sensitivity list
backends/verilog/verilog_backend.cc diff | blob | history