add LD bit-reversed unit test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 26 Jun 2021 17:42:56 +0000 (18:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 26 Jun 2021 17:42:56 +0000 (18:42 +0100)
commit8f224196e18dcea037ec6c8ea1b2e38e251fe401
tree07c6323901030fa33d4a26579ce065570df1b637
parentdefba3b634e1f2d506b3ec3c0b8baba20d62461c
add LD bit-reversed unit test
add LD/ST bit-reverse logic in ISACaller
src/openpower/decoder/helpers.py
src/openpower/decoder/isa/caller.py
src/openpower/decoder/isa/test_caller_svp64_ldst.py
src/openpower/decoder/power_fields.py
src/openpower/sv/trans/svp64.py