anv: Use genxml register support for L3 Cache config
authorJordan Justen <jordan.l.justen@intel.com>
Thu, 24 Mar 2016 20:05:04 +0000 (13:05 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Fri, 25 Mar 2016 07:19:18 +0000 (00:19 -0700)
commit8f3c23667433aacf5ad65a699c7ce082f3d6e416
tree092d42ed4d0e348973c244ab7cb1daa983ad4a1c
parent7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e
anv: Use genxml register support for L3 Cache config

The programming of the L3 Cache registers should match the previous
manually packed LRI values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
src/intel/vulkan/gen7_cmd_buffer.c
src/intel/vulkan/gen8_cmd_buffer.c