i965: Mark TCS URB writes as having side effects.
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 11 Jan 2016 20:25:12 +0000 (12:25 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 12 Jan 2016 20:19:47 +0000 (12:19 -0800)
commit9095847c254be2d55ab188232aa6b84555dbac4e
tree9316667c6e3e744a4cae806b47311a967b537b05
parent56fc2986d554b93d16fa1151765a9987bc42e4da
i965: Mark TCS URB writes as having side effects.

This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing
reads and writes from being incorrectly scheduled.

Fixes rendering in GFXBench 4.0's tessellation demo.

For some reason, we haven't ever listed URB writes as having
side-effects.  This hasn't been a problem because in most stages, we
never read from the URB, and only write to each location once.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93526
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
src/mesa/drivers/dri/i965/brw_shader.cpp