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(parent: f1a50a2) | patch
integration/soc: add clock_domain parameter to add_etherbone.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 8 May 2020 11:15:44 +0000 (13:15 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 8 May 2020 11:16:26 +0000 (13:16 +0200)
commit90c485fcc88751c8b123c9ae1f57319d9939f387
tree02591750b04addf75cc2c5b72213d15f9e1f2d90tree
parentf1a50a21388f5b6cabfa3bf0c481feade73957b9commit | diff
integration/soc: add clock_domain parameter to add_etherbone.

To allow using a sys_clk < 125MHz with a 1Gbps link.
litex/soc/integration/soc.py diff | blob | history