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(parent: 6251c95) | patch
fhdl.ir: record port direction explicitly.
authorwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 13:12:31 +0000 (13:12 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 13 Dec 2018 13:12:31 +0000 (13:12 +0000)
commit90f1503c918ccf5d7645f126cb03dc05dce47b00
treed1cae60d6209de40bb886ecf2a6031fcf8f0e8d5tree
parent6251c95d4e9822510b825edc624904f542ecb890commit | diff
fhdl.ir: record port direction explicitly.

No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
nmigen/back/rtlil.py diff | blob | history
nmigen/fhdl/ast.py diff | blob | history
nmigen/fhdl/ir.py diff | blob | history
nmigen/test/test_fhdl_ir.py diff | blob | history