Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
authorClifford Wolf <clifford@clifford.at>
Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)
committerGitHub <noreply@github.com>
Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)
commit9112850800a92ed0e330d8470e1273116d78ba14
treec09bc1be5d109b3270f217614b21f9ef3ca3490d
parentfd3d5cefad89a396c9807bf3b8dc7349c1a765f1
parent6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark

write_verilog: write RTLIL::Sa aka - as Verilog ?
backends/verilog/verilog_backend.cc