git.libre-soc.org Git - gem5.git/commit

author	Nilay Vaish <nilay@cs.wisc.edu>
	Fri, 14 Aug 2015 17:04:51 +0000 (12:04 -0500)
committer	Nilay Vaish <nilay@cs.wisc.edu>
	Fri, 14 Aug 2015 17:04:51 +0000 (12:04 -0500)
commit	91a84c5b3cfb888794ac0245c066a4724b9a0871
tree	79a8b41aff56655dbd187934d2709fdd7488c6ed	tree
parent	9ea5d9cad9381e05004de28ef25309ebe94c3a79	commit \| diff

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.

106 files changed:

src/cpu/testers/rubytest/Check.cc		diff \| blob \| history
src/cpu/testers/rubytest/Check.hh		diff \| blob \| history
src/cpu/testers/rubytest/CheckTable.cc		diff \| blob \| history
src/cpu/testers/rubytest/CheckTable.hh		diff \| blob \| history
src/cpu/testers/rubytest/RubyTester.hh		diff \| blob \| history
src/mem/protocol/MESI_Three_Level-L0cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Three_Level-L1cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Three_Level-msg.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-L1cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-L2cache.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-dir.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-dma.sm		diff \| blob \| history
src/mem/protocol/MESI_Two_Level-msg.sm		diff \| blob \| history
src/mem/protocol/MI_example-cache.sm		diff \| blob \| history
src/mem/protocol/MI_example-dir.sm		diff \| blob \| history
src/mem/protocol/MI_example-dma.sm		diff \| blob \| history
src/mem/protocol/MI_example-msg.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-L1cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-L2cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-dma.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_directory-msg.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-L1cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-L2cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-dma.sm		diff \| blob \| history
src/mem/protocol/MOESI_CMP_token-msg.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-cache.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-dir.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-dma.sm		diff \| blob \| history
src/mem/protocol/MOESI_hammer-msg.sm		diff \| blob \| history
src/mem/protocol/Network_test-cache.sm		diff \| blob \| history
src/mem/protocol/Network_test-dir.sm		diff \| blob \| history
src/mem/protocol/Network_test-msg.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_ComponentMapping.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_Defines.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_Exports.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_MemControl.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_Types.sm		diff \| blob \| history
src/mem/protocol/RubySlicc_Util.sm		diff \| blob \| history
src/mem/ruby/common/Address.cc		diff \| blob \| history
src/mem/ruby/common/Address.hh		diff \| blob \| history
src/mem/ruby/common/SubBlock.cc		diff \| blob \| history
src/mem/ruby/common/SubBlock.hh		diff \| blob \| history
src/mem/ruby/common/TypeDefines.hh		diff \| blob \| history
src/mem/ruby/filters/AbstractBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/BlockBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/BlockBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/BulkBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/BulkBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/GenericBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/GenericBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/H3BloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/H3BloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/LSB_CountingBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/LSB_CountingBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/MultiBitSelBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/MultiBitSelBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/MultiGrainBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/MultiGrainBloomFilter.hh		diff \| blob \| history
src/mem/ruby/filters/NonCountingBloomFilter.cc		diff \| blob \| history
src/mem/ruby/filters/NonCountingBloomFilter.hh		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.cc		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.hh		diff \| blob \| history
src/mem/ruby/profiler/AccessTraceForAddress.hh		diff \| blob \| history
src/mem/ruby/profiler/AddressProfiler.cc		diff \| blob \| history
src/mem/ruby/profiler/AddressProfiler.hh		diff \| blob \| history
src/mem/ruby/profiler/StoreTrace.cc		diff \| blob \| history
src/mem/ruby/profiler/StoreTrace.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/RubyRequest.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/RubyRequest.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/RubySlicc_Util.hh		diff \| blob \| history
src/mem/ruby/structures/CacheMemory.cc		diff \| blob \| history
src/mem/ruby/structures/CacheMemory.hh		diff \| blob \| history
src/mem/ruby/structures/DirectoryMemory.cc		diff \| blob \| history
src/mem/ruby/structures/DirectoryMemory.hh		diff \| blob \| history
src/mem/ruby/structures/MemoryNode.hh		diff \| blob \| history
src/mem/ruby/structures/PerfectCacheMemory.hh		diff \| blob \| history
src/mem/ruby/structures/PersistentTable.cc		diff \| blob \| history
src/mem/ruby/structures/PersistentTable.hh		diff \| blob \| history
src/mem/ruby/structures/Prefetcher.cc		diff \| blob \| history
src/mem/ruby/structures/Prefetcher.hh		diff \| blob \| history
src/mem/ruby/structures/RubyMemoryControl.cc		diff \| blob \| history
src/mem/ruby/structures/RubyMemoryControl.hh		diff \| blob \| history
src/mem/ruby/structures/TBETable.hh		diff \| blob \| history
src/mem/ruby/structures/TimerTable.cc		diff \| blob \| history
src/mem/ruby/structures/TimerTable.hh		diff \| blob \| history
src/mem/ruby/system/CacheRecorder.cc		diff \| blob \| history
src/mem/ruby/system/CacheRecorder.hh		diff \| blob \| history
src/mem/ruby/system/DMASequencer.cc		diff \| blob \| history
src/mem/ruby/system/DMASequencer.hh		diff \| blob \| history
src/mem/ruby/system/RubyPort.cc		diff \| blob \| history
src/mem/ruby/system/RubyPort.hh		diff \| blob \| history
src/mem/ruby/system/Sequencer.cc		diff \| blob \| history
src/mem/ruby/system/Sequencer.hh		diff \| blob \| history
src/mem/ruby/system/System.cc		diff \| blob \| history
src/mem/slicc/ast/ActionDeclAST.py		diff \| blob \| history
src/mem/slicc/ast/InPortDeclAST.py		diff \| blob \| history
src/mem/slicc/ast/StallAndWaitStatementAST.py		diff \| blob \| history
src/mem/slicc/symbols/StateMachine.py		diff \| blob \| history
src/mem/slicc/symbols/Type.py		diff \| blob \| history

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