misc: Standardize the way create() constructs SimObjects.
authorGabe Black <gabeblack@google.com>
Wed, 7 Oct 2020 13:49:23 +0000 (06:49 -0700)
committerGabe Black <gabeblack@google.com>
Wed, 14 Oct 2020 12:06:44 +0000 (12:06 +0000)
commit91d83cc8a12883f2d7493b37f50487cd7f03a9e6
tree5215657a132dc426de7ce16d6139e86ab4344b8c
parentaeb39c1441109c59915f657bccb2b5aeeb69fa34
misc: Standardize the way create() constructs SimObjects.

The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
822 files changed:
src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
src/arch/arm/fastmodel/CortexA76/evs.cc
src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
src/arch/arm/fastmodel/CortexR52/evs.cc
src/arch/arm/fastmodel/GIC/gic.cc
src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
src/arch/arm/fastmodel/iris/cpu.cc
src/arch/arm/fastmodel/iris/cpu.hh
src/arch/arm/fastmodel/iris/interrupts.cc
src/arch/arm/fastmodel/iris/interrupts.hh
src/arch/arm/fastmodel/iris/isa.cc
src/arch/arm/fastmodel/iris/isa.hh
src/arch/arm/fastmodel/iris/mmu.cc
src/arch/arm/fastmodel/iris/mmu.hh
src/arch/arm/fastmodel/iris/tlb.cc
src/arch/arm/fastmodel/iris/tlb.hh
src/arch/arm/freebsd/fs_workload.cc
src/arch/arm/freebsd/fs_workload.hh
src/arch/arm/freebsd/process.cc
src/arch/arm/freebsd/process.hh
src/arch/arm/fs_workload.cc
src/arch/arm/fs_workload.hh
src/arch/arm/interrupts.cc
src/arch/arm/interrupts.hh
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/arm/kvm/arm_cpu.cc
src/arch/arm/kvm/arm_cpu.hh
src/arch/arm/kvm/armv8_cpu.cc
src/arch/arm/kvm/armv8_cpu.hh
src/arch/arm/kvm/base_cpu.cc
src/arch/arm/kvm/base_cpu.hh
src/arch/arm/kvm/gic.cc
src/arch/arm/kvm/gic.hh
src/arch/arm/linux/fs_workload.cc
src/arch/arm/linux/fs_workload.hh
src/arch/arm/linux/process.cc
src/arch/arm/linux/process.hh
src/arch/arm/mmu.cc
src/arch/arm/mmu.hh
src/arch/arm/nativetrace.cc
src/arch/arm/nativetrace.hh
src/arch/arm/pmu.cc
src/arch/arm/pmu.hh
src/arch/arm/process.cc
src/arch/arm/process.hh
src/arch/arm/semihosting.cc
src/arch/arm/semihosting.hh
src/arch/arm/stage2_mmu.cc
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src/arch/arm/system.cc
src/arch/arm/system.hh
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/arch/arm/tlb.cc
src/arch/arm/tlb.hh
src/arch/arm/tracers/tarmac_parser.cc
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src/arch/arm/tracers/tarmac_tracer.cc
src/arch/arm/tracers/tarmac_tracer.hh
src/arch/generic/interrupts.hh
src/arch/generic/mmu.hh
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src/arch/mips/interrupts.cc
src/arch/mips/interrupts.hh
src/arch/mips/isa.cc
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src/arch/mips/linux/process.cc
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src/arch/mips/mmu.cc
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src/arch/mips/process.cc
src/arch/mips/process.hh
src/arch/mips/tlb.cc
src/arch/mips/tlb.hh
src/arch/power/interrupts.cc
src/arch/power/interrupts.hh
src/arch/power/isa.cc
src/arch/power/isa.hh
src/arch/power/linux/process.cc
src/arch/power/linux/process.hh
src/arch/power/mmu.cc
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src/arch/power/process.cc
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src/arch/power/tlb.cc
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src/arch/riscv/bare_metal/fs_workload.cc
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src/arch/riscv/interrupts.cc
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src/arch/riscv/isa.cc
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src/arch/riscv/linux/process.cc
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src/arch/riscv/pagetable_walker.cc
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src/arch/riscv/process.cc
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src/arch/riscv/tlb.cc
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src/arch/sparc/interrupts.cc
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src/arch/sparc/isa.cc
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src/arch/sparc/linux/process.cc
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src/arch/sparc/mmu.cc
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src/arch/sparc/nativetrace.cc
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src/arch/sparc/process.cc
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src/arch/sparc/solaris/process.cc
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src/arch/sparc/tlb.cc
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src/arch/x86/bios/acpi.cc
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src/arch/x86/bios/e820.cc
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src/arch/x86/bios/intelmp.cc
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src/arch/x86/bios/smbios.cc
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src/arch/x86/fs_workload.cc
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src/arch/x86/interrupts.cc
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src/arch/x86/isa.cc
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src/arch/x86/linux/fs_workload.cc
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src/arch/x86/linux/process.cc
src/arch/x86/mmu.cc
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src/cpu/intr_control_noisa.cc
src/cpu/kvm/base.cc
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src/cpu/kvm/vm.cc
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src/cpu/kvm/x86_cpu.cc
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src/cpu/minor/cpu.cc
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src/cpu/minor/pipeline.cc
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src/cpu/nativetrace.cc
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src/cpu/o3/deriv.cc
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src/cpu/o3/fu_pool.cc
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src/cpu/o3/iew.hh
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src/cpu/o3/inst_queue.hh
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src/cpu/o3/probe/elastic_trace.cc
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src/cpu/o3/probe/simple_trace.cc
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src/cpu/o3/rename.hh
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src/cpu/pred/2bit_local.cc
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src/cpu/pred/bi_mode.cc
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src/cpu/pred/bpred_unit.cc
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src/cpu/pred/multiperspective_perceptron_64KB.cc
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src/cpu/pred/multiperspective_perceptron_tage.cc
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src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
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src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
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src/cpu/pred/simple_indirect.cc
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src/cpu/pred/statistical_corrector.cc
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src/cpu/pred/tournament.cc
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src/cpu/simple/NonCachingSimpleCPU.py
src/cpu/simple/atomic.cc
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src/cpu/simple/probes/simpoint.cc
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src/cpu/simple/timing.cc
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src/cpu/testers/directedtest/DirectedGenerator.cc
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src/cpu/testers/directedtest/InvalidateGenerator.cc
src/cpu/testers/directedtest/InvalidateGenerator.hh
src/cpu/testers/directedtest/RubyDirectedTester.cc
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src/cpu/testers/directedtest/SeriesRequestGenerator.cc
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src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
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src/cpu/testers/memtest/memtest.cc
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src/cpu/testers/rubytest/RubyTester.cc
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src/cpu/testers/traffic_gen/pygen.cc
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src/cpu/testers/traffic_gen/stream_gen.cc
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src/cpu/timing_expr.cc
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src/cpu/trace/trace_cpu.cc
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src/dev/arm/a9scu.cc
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src/dev/arm/abstract_nvm.hh
src/dev/arm/amba_device.cc
src/dev/arm/amba_device.hh
src/dev/arm/amba_fake.cc
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src/dev/arm/base_gic.cc
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src/dev/arm/display.cc
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src/dev/arm/energy_ctrl.cc
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src/dev/arm/flash_device.cc
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src/dev/arm/fvp_base_pwr_ctrl.cc
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src/dev/arm/generic_timer.cc
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src/dev/arm/gpu_nomali.cc
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src/dev/arm/hdlcd.cc
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src/dev/arm/realview.cc
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src/dev/arm/rtc_pl031.cc
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src/dev/arm/rv_ctrl.cc
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src/dev/arm/smmu_v3.cc
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src/gpu-compute/scheduler.cc
src/gpu-compute/scheduler.hh
src/gpu-compute/scoreboard_check_stage.cc
src/gpu-compute/scoreboard_check_stage.hh
src/gpu-compute/shader.cc
src/gpu-compute/shader.hh
src/gpu-compute/simple_pool_manager.cc
src/gpu-compute/simple_pool_manager.hh
src/gpu-compute/tlb_coalescer.cc
src/gpu-compute/tlb_coalescer.hh
src/gpu-compute/vector_register_file.cc
src/gpu-compute/vector_register_file.hh
src/gpu-compute/wavefront.cc
src/gpu-compute/wavefront.hh
src/learning_gem5/part2/goodbye_object.cc
src/learning_gem5/part2/goodbye_object.hh
src/learning_gem5/part2/hello_object.cc
src/learning_gem5/part2/hello_object.hh
src/learning_gem5/part2/simple_cache.cc
src/learning_gem5/part2/simple_cache.hh
src/learning_gem5/part2/simple_memobj.cc
src/learning_gem5/part2/simple_memobj.hh
src/learning_gem5/part2/simple_object.cc
src/learning_gem5/part2/simple_object.hh
src/mem/abstract_mem.cc
src/mem/abstract_mem.hh
src/mem/addr_mapper.cc
src/mem/addr_mapper.hh
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache.cc
src/mem/cache/cache.hh
src/mem/cache/compressors/base.cc
src/mem/cache/compressors/base.hh
src/mem/cache/compressors/base_delta.cc
src/mem/cache/compressors/base_delta.hh
src/mem/cache/compressors/base_delta_impl.hh
src/mem/cache/compressors/base_dictionary_compressor.cc
src/mem/cache/compressors/cpack.cc
src/mem/cache/compressors/cpack.hh
src/mem/cache/compressors/dictionary_compressor.hh
src/mem/cache/compressors/dictionary_compressor_impl.hh
src/mem/cache/compressors/fpcd.cc
src/mem/cache/compressors/fpcd.hh
src/mem/cache/compressors/multi.cc
src/mem/cache/compressors/multi.hh
src/mem/cache/compressors/perfect.cc
src/mem/cache/compressors/perfect.hh
src/mem/cache/compressors/repeated_qwords.cc
src/mem/cache/compressors/repeated_qwords.hh
src/mem/cache/compressors/zero.cc
src/mem/cache/compressors/zero.hh
src/mem/cache/noncoherent_cache.cc
src/mem/cache/noncoherent_cache.hh
src/mem/cache/prefetch/access_map_pattern_matching.cc
src/mem/cache/prefetch/access_map_pattern_matching.hh
src/mem/cache/prefetch/base.cc
src/mem/cache/prefetch/base.hh
src/mem/cache/prefetch/bop.cc
src/mem/cache/prefetch/bop.hh
src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
src/mem/cache/prefetch/indirect_memory.cc
src/mem/cache/prefetch/indirect_memory.hh
src/mem/cache/prefetch/irregular_stream_buffer.cc
src/mem/cache/prefetch/irregular_stream_buffer.hh
src/mem/cache/prefetch/multi.cc
src/mem/cache/prefetch/multi.hh
src/mem/cache/prefetch/pif.cc
src/mem/cache/prefetch/pif.hh
src/mem/cache/prefetch/queued.cc
src/mem/cache/prefetch/queued.hh
src/mem/cache/prefetch/sbooe.cc
src/mem/cache/prefetch/sbooe.hh
src/mem/cache/prefetch/signature_path.cc
src/mem/cache/prefetch/signature_path.hh
src/mem/cache/prefetch/signature_path_v2.cc
src/mem/cache/prefetch/signature_path_v2.hh
src/mem/cache/prefetch/slim_ampm.cc
src/mem/cache/prefetch/slim_ampm.hh
src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
src/mem/cache/prefetch/stride.cc
src/mem/cache/prefetch/stride.hh
src/mem/cache/prefetch/tagged.cc
src/mem/cache/prefetch/tagged.hh
src/mem/cache/replacement_policies/base.hh
src/mem/cache/replacement_policies/bip_rp.cc
src/mem/cache/replacement_policies/bip_rp.hh
src/mem/cache/replacement_policies/brrip_rp.cc
src/mem/cache/replacement_policies/brrip_rp.hh
src/mem/cache/replacement_policies/fifo_rp.cc
src/mem/cache/replacement_policies/fifo_rp.hh
src/mem/cache/replacement_policies/lfu_rp.cc
src/mem/cache/replacement_policies/lfu_rp.hh
src/mem/cache/replacement_policies/lru_rp.cc
src/mem/cache/replacement_policies/lru_rp.hh
src/mem/cache/replacement_policies/mru_rp.cc
src/mem/cache/replacement_policies/mru_rp.hh
src/mem/cache/replacement_policies/random_rp.cc
src/mem/cache/replacement_policies/random_rp.hh
src/mem/cache/replacement_policies/second_chance_rp.cc
src/mem/cache/replacement_policies/second_chance_rp.hh
src/mem/cache/replacement_policies/tree_plru_rp.cc
src/mem/cache/replacement_policies/tree_plru_rp.hh
src/mem/cache/replacement_policies/weighted_lru_rp.cc
src/mem/cache/replacement_policies/weighted_lru_rp.hh
src/mem/cache/tags/base.cc
src/mem/cache/tags/base.hh
src/mem/cache/tags/base_set_assoc.cc
src/mem/cache/tags/base_set_assoc.hh
src/mem/cache/tags/compressed_tags.cc
src/mem/cache/tags/compressed_tags.hh
src/mem/cache/tags/fa_lru.cc
src/mem/cache/tags/fa_lru.hh
src/mem/cache/tags/indexing_policies/base.cc
src/mem/cache/tags/indexing_policies/base.hh
src/mem/cache/tags/indexing_policies/set_associative.cc
src/mem/cache/tags/indexing_policies/set_associative.hh
src/mem/cache/tags/indexing_policies/skewed_associative.cc
src/mem/cache/tags/indexing_policies/skewed_associative.hh
src/mem/cache/tags/sector_tags.cc
src/mem/cache/tags/sector_tags.hh
src/mem/coherent_xbar.cc
src/mem/coherent_xbar.hh
src/mem/comm_monitor.cc
src/mem/comm_monitor.hh
src/mem/drampower.cc
src/mem/drampower.hh
src/mem/dramsim2.cc
src/mem/dramsim2.hh
src/mem/dramsim3.cc
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src/mem/external_master.cc
src/mem/external_master.hh
src/mem/external_slave.cc
src/mem/external_slave.hh
src/mem/hmc_controller.cc
src/mem/hmc_controller.hh
src/mem/mem_checker.cc
src/mem/mem_checker.hh
src/mem/mem_checker_monitor.cc
src/mem/mem_checker_monitor.hh
src/mem/mem_ctrl.cc
src/mem/mem_ctrl.hh
src/mem/mem_delay.cc
src/mem/mem_delay.hh
src/mem/mem_interface.cc
src/mem/mem_interface.hh
src/mem/mem_object.hh
src/mem/noncoherent_xbar.cc
src/mem/noncoherent_xbar.hh
src/mem/probes/base.cc
src/mem/probes/base.hh
src/mem/probes/mem_footprint.cc
src/mem/probes/mem_footprint.hh
src/mem/probes/mem_trace.cc
src/mem/probes/mem_trace.hh
src/mem/probes/stack_dist.cc
src/mem/probes/stack_dist.hh
src/mem/qos/mem_ctrl.cc
src/mem/qos/mem_ctrl.hh
src/mem/qos/mem_sink.cc
src/mem/qos/mem_sink.hh
src/mem/qos/policy.cc
src/mem/qos/policy.hh
src/mem/qos/policy_fixed_prio.cc
src/mem/qos/policy_fixed_prio.hh
src/mem/qos/policy_pf.cc
src/mem/qos/policy_pf.hh
src/mem/qos/q_policy.cc
src/mem/qos/q_policy.hh
src/mem/qos/turnaround_policy.hh
src/mem/qos/turnaround_policy_ideal.cc
src/mem/qos/turnaround_policy_ideal.hh
src/mem/ruby/network/BasicLink.cc
src/mem/ruby/network/BasicLink.hh
src/mem/ruby/network/BasicRouter.cc
src/mem/ruby/network/BasicRouter.hh
src/mem/ruby/network/MessageBuffer.cc
src/mem/ruby/network/MessageBuffer.hh
src/mem/ruby/network/Network.cc
src/mem/ruby/network/Network.hh
src/mem/ruby/network/Topology.cc
src/mem/ruby/network/fault_model/FaultModel.cc
src/mem/ruby/network/fault_model/FaultModel.hh
src/mem/ruby/network/garnet/CreditLink.hh
src/mem/ruby/network/garnet/GarnetLink.cc
src/mem/ruby/network/garnet/GarnetLink.hh
src/mem/ruby/network/garnet/GarnetNetwork.cc
src/mem/ruby/network/garnet/GarnetNetwork.hh
src/mem/ruby/network/garnet/NetworkBridge.cc
src/mem/ruby/network/garnet/NetworkBridge.hh
src/mem/ruby/network/garnet/NetworkInterface.cc
src/mem/ruby/network/garnet/NetworkInterface.hh
src/mem/ruby/network/garnet/NetworkLink.cc
src/mem/ruby/network/garnet/NetworkLink.hh
src/mem/ruby/network/garnet/Router.cc
src/mem/ruby/network/garnet/Router.hh
src/mem/ruby/network/simple/SimpleLink.cc
src/mem/ruby/network/simple/SimpleLink.hh
src/mem/ruby/network/simple/SimpleNetwork.cc
src/mem/ruby/network/simple/SimpleNetwork.hh
src/mem/ruby/network/simple/Switch.cc
src/mem/ruby/network/simple/Switch.hh
src/mem/ruby/profiler/Profiler.cc
src/mem/ruby/profiler/Profiler.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/ruby/structures/CacheMemory.cc
src/mem/ruby/structures/CacheMemory.hh
src/mem/ruby/structures/DirectoryMemory.cc
src/mem/ruby/structures/DirectoryMemory.hh
src/mem/ruby/structures/RubyPrefetcher.cc
src/mem/ruby/structures/RubyPrefetcher.hh
src/mem/ruby/structures/WireBuffer.cc
src/mem/ruby/structures/WireBuffer.hh
src/mem/ruby/system/DMASequencer.cc
src/mem/ruby/system/DMASequencer.hh
src/mem/ruby/system/GPUCoalescer.cc
src/mem/ruby/system/GPUCoalescer.hh
src/mem/ruby/system/HTMSequencer.cc
src/mem/ruby/system/HTMSequencer.hh
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/ruby/system/RubyPortProxy.cc
src/mem/ruby/system/RubyPortProxy.hh
src/mem/ruby/system/RubySystem.cc
src/mem/ruby/system/RubySystem.hh
src/mem/ruby/system/Sequencer.cc
src/mem/ruby/system/Sequencer.hh
src/mem/ruby/system/VIPERCoalescer.cc
src/mem/ruby/system/VIPERCoalescer.hh
src/mem/serial_link.cc
src/mem/serial_link.hh
src/mem/simple_mem.cc
src/mem/simple_mem.hh
src/mem/slicc/symbols/StateMachine.py
src/mem/snoop_filter.cc
src/mem/snoop_filter.hh
src/mem/xbar.cc
src/mem/xbar.hh
src/python/m5/SimObject.py
src/sim/clock_domain.cc
src/sim/clock_domain.hh
src/sim/clocked_object.cc
src/sim/clocked_object.hh
src/sim/dvfs_handler.cc
src/sim/dvfs_handler.hh
src/sim/emul_driver.hh
src/sim/insttracer.hh
src/sim/kernel_workload.cc
src/sim/power/mathexpr_powermodel.cc
src/sim/power/mathexpr_powermodel.hh
src/sim/power/power_model.cc
src/sim/power/power_model.hh
src/sim/power/thermal_domain.cc
src/sim/power/thermal_domain.hh
src/sim/power/thermal_model.cc
src/sim/power/thermal_model.hh
src/sim/power/thermal_node.cc
src/sim/power/thermal_node.hh
src/sim/power_domain.cc
src/sim/power_domain.hh
src/sim/power_state.cc
src/sim/power_state.hh
src/sim/probe/probe.cc
src/sim/probe/probe.hh
src/sim/process.cc
src/sim/process.hh
src/sim/pseudo_inst.cc
src/sim/redirect_path.cc
src/sim/redirect_path.hh
src/sim/root.cc
src/sim/root.hh
src/sim/se_workload.cc
src/sim/sim_object.cc
src/sim/sim_object.hh
src/sim/sub_system.cc
src/sim/sub_system.hh
src/sim/system.cc
src/sim/system.hh
src/sim/ticked_object.cc
src/sim/ticked_object.hh
src/sim/voltage_domain.cc
src/sim/voltage_domain.hh
src/sim/workload.hh
src/systemc/core/kernel.cc
src/systemc/core/kernel.hh
src/systemc/tlm_bridge/gem5_to_tlm.cc
src/systemc/tlm_bridge/gem5_to_tlm.hh
src/systemc/tlm_bridge/tlm_to_gem5.cc
src/systemc/tlm_bridge/tlm_to_gem5.hh