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(parent: 0129d41) | patch
Improved scope resolution of local regs in Verilog+AST frontend
authorClifford Wolf <clifford@clifford.at>
Tue, 5 Aug 2014 10:15:53 +0000 (12:15 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 5 Aug 2014 10:15:53 +0000 (12:15 +0200)
commit91dd87e60b120119ee34a9961a7b5f33f340282e
treea7e110f443798bc0ef3c070aec0435d3c5e6b02ctree
parent0129d41efad623ee95878a673c1c1190261ba3efcommit | diff
Improved scope resolution of local regs in Verilog+AST frontend
frontends/ast/ast.h diff | blob | history
frontends/ast/simplify.cc diff | blob | history
frontends/verilog/parser.y diff | blob | history
tests/simple/scopes.v [new file with mode: 0644] blob