projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Wed, 18 Dec 2013 12:21:02 +0000 (13:21 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Wed, 18 Dec 2013 12:21:02 +0000 (13:21 +0100) | ||
| commit | 921064c20044f72a64bec12dbd73103bdd3f45e3 | |
| tree | b1b7e24b7756f45c66a617afc17496711afc0d33 | tree |
| parent | 09bd82db217d27930d1eeec8d0dfd1e014c675b4 | commit | diff |
| frontends/verilog/preproc.cc | diff | blob | history | |
| tests/simple/macros.v | [new file with mode: 0644] | blob |