Added read-enable to memory model
authorClifford Wolf <clifford@clifford.at>
Fri, 25 Sep 2015 10:23:11 +0000 (12:23 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 25 Sep 2015 10:23:11 +0000 (12:23 +0200)
commit924d9d6e86a5e9a2294479345daac1c03d78008a
tree04d28a2068b32c44c0aca2b8b815f6fc51cec427
parentec92c8965960fa814c3663e987bc2a7eb80965e5
Added read-enable to memory model
17 files changed:
frontends/ast/genrtlil.cc
frontends/verific/verific.cc
kernel/celltypes.h
kernel/rtlil.cc
manual/CHAPTER_CellLib.tex
passes/memory/memory_bram.cc
passes/memory/memory_collect.cc
passes/memory/memory_dff.cc
passes/memory/memory_map.cc
passes/memory/memory_unpack.cc
techlibs/common/simlib.v
techlibs/ice40/brams.txt
techlibs/ice40/brams_map.v
techlibs/xilinx/brams.txt
techlibs/xilinx/brams_map.v
techlibs/xilinx/synth_xilinx.cc
tests/techmap/mem_simple_4x1_map.v