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(parent: 9343c93) | patch
lima/ppir: fix alignment on regalloc spilling loads
authorErico Nunes <nunes.erico@gmail.com>
Sun, 21 Jul 2019 22:55:24 +0000 (00:55 +0200)
committerErico Nunes <nunes.erico@gmail.com>
Tue, 23 Jul 2019 08:24:19 +0000 (08:24 +0000)
commit9254059dd859d6bb8820525910ec028098e788e8
tree94e19b9d62a270675fd5e9ef4d340ee1de8614b2tree
parent9343c93e34b559d29f62209ed832f9f11773515acommit | diff
lima/ppir: fix alignment on regalloc spilling loads

The spilling code spills entire vec4 registers regardless of the
components used by the spilled uses.
The inserted stores code force the 4 components, but these loads were
using a variable number of components, causing bugs on loading the
spilled registers.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
src/gallium/drivers/lima/ir/pp/regalloc.c diff | blob | history