Merge pull request #1203 from whitequark/write_verilog-zero-width-values
authorClifford Wolf <clifford@clifford.at>
Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)
committerGitHub <noreply@github.com>
Thu, 18 Jul 2019 13:31:27 +0000 (15:31 +0200)
commit927f0caa9d70ccf3634b29d8558c78febcc9081c
treec34e46ade9cd99dc38eff34b2b71574464b4b64c
parent56c00e871fbb73649d3b6f7ccee31c90942a020c
parent4ff44d85a5cb63c7b3f67c2f2398e62db7f199eb
Merge pull request #1203 from whitequark/write_verilog-zero-width-values

write_verilog: dump zero width constants correctly
backends/verilog/verilog_backend.cc