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(parent: 217360a) | patch
Wire directly to the Wishbone bus, making simulations faster and reduce the chances...
authorJean THOMAS <git0@pub.jeanthomas.me>
Mon, 27 Jul 2020 12:02:04 +0000 (14:02 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Mon, 27 Jul 2020 12:02:04 +0000 (14:02 +0200)
commit92817c240451c1d14d78bdf432afbe1b6756843d
tree4b45acfe1419e1ce3d975ff69553dce83240c193tree
parent217360adae36097eb7daa364a55a570a57647600commit | diff
Wire directly to the Wishbone bus, making simulations faster and reduce the chances of reading before ACK
gram/simulation/simsoc.py diff | blob | history
gram/simulation/simsoctb.v diff | blob | history
gram/simulation/uartbridge.py [deleted file] blob | history