RISC-V: Prohibit combination of 'E' and 'H'

RISC-V: Prohibit combination of 'E' and 'H'

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and
	'H' combinations.

gas/ChangeLog:

	* testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to
	make sure that RV32E + 'H' is prohibited.
	* testsuite/gas/riscv/march-fail-rv32eh.l: Likewise.