arch-arm: adding register control flags enabling LSE implementation
authorJordi Vaquero <jordi.vaquero@metempsy.com>
Tue, 6 Aug 2019 13:49:14 +0000 (15:49 +0200)
committerJordi Vaquero <jordi.vaquero@metempsy.com>
Wed, 7 Aug 2019 14:30:51 +0000 (14:30 +0000)
commit92abad849186256f4a4b309ed867d375d07c5c63
tree757b4fb7225fe35d8739ad2950aaa51042a362f2
parent676d5fe4e882c9d073964a72c619024306fd279a
arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/ArmSystem.py
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/arm/system.cc
src/arch/arm/system.hh