sim: default runner to Icarus Verilog
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 9 Feb 2013 16:04:53 +0000 (17:04 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 9 Feb 2013 16:04:53 +0000 (17:04 +0100)
commit92b67df41c49bffa4a65fa990b60ee13c29ad8f7
tree1f74401d2bf463ec437b86ee62496134625f538c
parentbd6856ba7a674baa5b3d072ee3df555acb62d54d
sim: default runner to Icarus Verilog
13 files changed:
doc/simulation.rst
examples/dataflow/dma.py
examples/dataflow/misc.py
examples/dataflow/structuring.py
examples/pytholite/basic.py
examples/pytholite/uio.py
examples/sim/abstract_transactions.py
examples/sim/basic1.py
examples/sim/basic2.py
examples/sim/dataflow.py
examples/sim/fir.py
examples/sim/memory.py
migen/sim/generic.py