Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
authorEddie Hung <eddie@fpgeh.com>
Wed, 28 Aug 2019 17:51:39 +0000 (10:51 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 28 Aug 2019 17:51:39 +0000 (10:51 -0700)
commit9314a0a42ec05e82d2d3d77aebddfb06271a4730
tree9251ba658029484731a53e68bd8e14d2c5f8a3e8
parent13424352cc8dca5f08ad22aa42066dc7f62afea5
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
techlibs/xilinx/cells_sim.v