git.libre-soc.org Git - yosys.git/commit

author	Marcelina Kościelnicka <mwk@0x04.net>
	Mon, 24 Jan 2022 15:02:29 +0000 (16:02 +0100)
committer	Marcelina Kościelnicka <mwk@0x04.net>
	Fri, 28 Jan 2022 22:34:41 +0000 (23:34 +0100)
commit	93508d58dafbbffcedffa70b21a197b6fca8bb30
tree	4f4bed22749559a1938457015ff875891fd7a40a	tree
parent	db33b1e535f5ee93dba9ee1cc181b91c482a4dee	commit \| diff

Add $bmux and $demux cells.

25 files changed:

backends/btor/btor.cc		diff \| blob \| history
backends/cxxrtl/cxxrtl.h		diff \| blob \| history
backends/cxxrtl/cxxrtl_backend.cc		diff \| blob \| history
backends/firrtl/firrtl.cc		diff \| blob \| history
backends/smt2/smt2.cc		diff \| blob \| history
backends/smv/smv.cc		diff \| blob \| history
backends/verilog/verilog_backend.cc		diff \| blob \| history
kernel/calc.cc		diff \| blob \| history
kernel/celledges.cc		diff \| blob \| history
kernel/celltypes.h		diff \| blob \| history
kernel/consteval.h		diff \| blob \| history
kernel/qcsat.cc		diff \| blob \| history
kernel/rtlil.cc		diff \| blob \| history
kernel/rtlil.h		diff \| blob \| history
kernel/satgen.cc		diff \| blob \| history
passes/cmds/clean_zerowidth.cc		diff \| blob \| history
passes/cmds/stat.cc		diff \| blob \| history
passes/sat/sim.cc		diff \| blob \| history
passes/techmap/Makefile.inc		diff \| blob \| history
passes/techmap/bmuxmap.cc	[new file with mode: 0644]	blob
passes/techmap/demuxmap.cc	[new file with mode: 0644]	blob
passes/techmap/simplemap.cc		diff \| blob \| history
passes/tests/test_cell.cc		diff \| blob \| history
techlibs/common/simlib.v		diff \| blob \| history
techlibs/common/techmap.v		diff \| blob \| history