i965: Have NIR lower flrp on pre-GEN6 vec4 backend
authorIan Romanick <ian.d.romanick@intel.com>
Mon, 7 Mar 2016 18:55:21 +0000 (10:55 -0800)
committerIan Romanick <ian.d.romanick@intel.com>
Tue, 22 Mar 2016 21:42:42 +0000 (14:42 -0700)
commit9442db4f89156713bcb241803f6de7c0777262c5
tree5c1f865b90f12115a1c0623bb647efd1cdf244a9
parent18c5fa1122eddc2da0912749760356e570631163
i965: Have NIR lower flrp on pre-GEN6 vec4 backend

Previously we were doing the lowering by hand in vec4_visitor::emit_lrp.
By doing it in NIR, we have the opportunity for NIR to do additional
optimization of the expanded code.

This also enables optimizations added by the next commit.

shader-db results:

G4X / Ironlake
total instructions in shared programs: 4024401 -> 4016538 (-0.20%)
instructions in affected programs: 447686 -> 439823 (-1.76%)
helped: 2623
HURT: 0

total cycles in shared programs: 84375846 -> 84328296 (-0.06%)
cycles in affected programs: 16964960 -> 16917410 (-0.28%)
helped: 2556
HURT: 41

Unsurprisingly, no changes on later platforms.

v2: Formatting and comment changes suggested by Matt.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_compiler.c