Pl011: Added registers UART_RSR/UART_ECR
authorMaurice Becker <madnaurice@googlemail.com>
Tue, 18 Sep 2018 08:27:40 +0000 (10:27 +0200)
committerMadMaurice <madnaurice@googlemail.com>
Tue, 18 Sep 2018 09:58:46 +0000 (09:58 +0000)
commit95143897fc9894241c663982496578b67a238be7
tree920eb601f983f5f68019d20d58b609d9dc84001e
parent1fdf576ec73f676c1bfa2e2524293deab0f5cd68
Pl011: Added registers UART_RSR/UART_ECR

UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4).  As
these transmission errors never occur, they are implemented as RAZ/WI.

Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.

Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/dev/arm/pl011.cc
src/dev/arm/pl011.hh