[AArch64] Rearrange SVE conversion patterns

[AArch64] Rearrange SVE conversion patterns

The SVE int<->float conversion patterns need to handle various
combinations of modes, making sure that the predicate mode is based
on the widest element size.  We did this using separate patterns for
conversions involving:

- HF (converting to/from [HSD]I, predicated based on the int operand)
- SF (converting to/from [SD]I, predicated based on the int operand)
- DF (converting to/from [SD]I, predicated based on the float operand)

This worked, and meant that there were no redundant patterns.  However,
the ACLE needs various new predicated patterns too, and having three
versions of each one seemed excessive.

This patch instead splits the patterns into two groups rather than three.
For conversions to integers:

- truncating (predicated based on the source type, DF->SI only)
- non-truncating (predicated based on the destination type)

For conversions from integers:

- extending (predicated based on the destination type, SI->DF only)
- non-extending (predicated based on the source type)

This means that we still don't create pattern names for the invalid
combinations DF<->HI and SF<->HI.  The downside is that we need to
use C conditions to exclude the SI<->DF case from the non-truncating/
non-extending patterns.  We therefore have two pattern names for SI<->DF,
but genconditions ensures that the invalid one always has the value
CODE_FOR_nothing.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (VNx4SI_ONLY, VNx2DF_ONLY): New mode
	iterators.
	(SVE_BHSI, SVE_SDI): Tweak comment.
	(SVE_HSDI): Likewise.  Fix definition.
	(SVE_SDF): New mode iterator.
	(elem_bits): New mode attribute.
	(SVE_COND_FCVT): New int iterator.
	* config/aarch64/aarch64-sve.md
	(*<SVE_COND_ICVTF:optab>v16hsf<SVE_HSDI:mode>2)
	(*<SVE_COND_ICVTF:optab>vnx4sf<SVE_SDI:mode>2)
	(*<SVE_COND_ICVTF:optab>vnx2df<SVE_SDI:mode>2): Merge into...
	(*aarch64_sve_<SVE_COND_ICVTF:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
	(*aarch64_sve_<SVE_COND_ICVTF:optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
	...these new patterns.
	(*<SVE_COND_FCVTI:optab><SVE_HSDI:mode>vnx8hf2)
	(*<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx4sf2)
	(aarch64_sve_<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx2df2):
	Merge into...
	(*aarch64_sve_<SVE_COND_FCVTI:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>)
	(aarch64_sve_<SVE_COND_FCVTI:optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>):
	...these new patterns.
	(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Update accordingly.
	(*trunc<Vwide><SVE_SDF:mode>2): Replace with...
	(*aarch64_sve_<SVE_COND_FCVT:optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>):
	...this new pattern.
	(aarch64_sve_extend<SVE_HSDF:mode><Vwide>2): Replace with...
	(aarch64_sve_<SVE_COND_FCVT:optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>):
	...this new pattern.
	(vec_unpacks_<perm_hilo>_<mode>): Update accordingly.

From-SVN: r274424