mem-cache: alias to mem::getMasterPort in TLB class
authorAndrea Mondelli <Andrea.Mondelli@ucf.edu>
Fri, 22 Feb 2019 16:29:10 +0000 (11:29 -0500)
committerAndrea Mondelli <Andrea.Mondelli@ucf.edu>
Fri, 1 Mar 2019 16:46:47 +0000 (16:46 +0000)
commit96cc03f90db82fa8f84248ef478362267dba292c
tree973f9dad0038300ba7fd761c3ef2cbfb1e56bf67
parenta7eebbfa693e3fa55c0a9c876b97adcf72662c71
mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/arch/arm/tlb.cc
src/arch/arm/tlb.hh
src/arch/generic/tlb.hh
src/arch/x86/tlb.cc
src/arch/x86/tlb.hh
src/cpu/base.cc