arch-riscv: Fix disassembling of all register instructions
authorIan Jiang <ianjiang.ict@gmail.com>
Fri, 14 Aug 2020 02:13:41 +0000 (10:13 +0800)
committerIan Jiang <ianjiang.ict@gmail.com>
Tue, 18 Aug 2020 01:11:15 +0000 (01:11 +0000)
commit96f482fd6cc01f9181360daac0ae80e2dee40401
tree1eac4017734530d1e53a8906ff02f58d17ca7d86
parentbfc3967695f6184e7c326c058c4a91fd77473c0d
arch-riscv: Fix disassembling of all register instructions

How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.

This patch fixes the problem.

Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/insts/standard.cc