sv: improve support for wire and var with user-defined types
authorBrett Witherspoon <brett@witherspoondesign.com>
Tue, 22 Jun 2021 14:51:41 +0000 (09:51 -0500)
committerZachary Snow <zachary.j.snow@gmail.com>
Fri, 13 Aug 2021 04:41:41 +0000 (22:41 -0600)
commit979053855c85b72c6344bf6350fb9a8360f3d092
treeffe80454cbe9dfd862ea93f93124533e38fe4fae
parentc8023e37d82adffd0c0ba54575c949be9da45198
sv: improve support for wire and var with user-defined types

- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
frontends/verilog/verilog_parser.y
tests/svtypes/typedef_initial_and_assign.sv [new file with mode: 0644]
tests/svtypes/typedef_initial_and_assign.ys [new file with mode: 0644]