Added RTLIL::Cell::has(portname)
authorClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 14:11:28 +0000 (16:11 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 14:11:28 +0000 (16:11 +0200)
commit97a59851a6c411ccb06162d4b31725bf89262378
tree74cba570ab858657b6fa524cdc9fa45b0493c4be
parenta84cb0493566f8f5eb610c6d7b67dda85b0f227b
Added RTLIL::Cell::has(portname)
12 files changed:
backends/spice/spice.cc
backends/verilog/verilog_backend.cc
frontends/ilang/parser.y
kernel/consteval.h
kernel/rtlil.cc
kernel/rtlil.h
passes/cmds/add.cc
passes/fsm/fsm_detect.cc
passes/fsm/fsm_expand.cc
passes/fsm/fsm_extract.cc
passes/opt/opt_const.cc
passes/sat/expose.cc