tests: read +/xilinx/cell_sim.v before xilinx_dsp test
authorEddie Hung <eddie@fpgeh.com>
Thu, 23 Apr 2020 00:50:30 +0000 (17:50 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 23 Apr 2020 00:50:30 +0000 (17:50 -0700)
commit988d47af8533a0c7728095862dbc6a7311c1f8b7
tree1574fa5d122982cdf43ae120630eb5c82bda35f3
parent592baebd22ab1c80512b6f91926d90b33393285e
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
tests/arch/xilinx/xilinx_dsp.ys