Update for new memory system. Uses the ports to access memory now. Also supports...

Update for new memory system.  Uses the ports to access memory now.  Also supports the response path of the new memory system, as well as retrying accesses.

cpu/simple/cpu.cc:
    Update for new memory system.  Supports using ports to access the memory system.  The IcacheMissStall/DcacheMissStall statuses have been changed to reflect the cache returning a response after a variable latency (due to hit/miss).  They are now DcacheWaitResponse/IcacheWaitResponse.  Also supports retrying accesses.

    For now the body of the copy functions are commented out.
cpu/simple/cpu.hh:
    Update for new memory system.

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extra : convert_revision : 5a80247537d98ed690f7b6119094d9f59b4c7d73