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(parent: d062a82) | patch
fastmodel: Ensure unset vec reg bits are zero/false.
authorGabe Black <gabeblack@google.com>
Tue, 14 Jan 2020 01:00:41 +0000 (17:00 -0800)
committerGabe Black <gabeblack@google.com>
Thu, 6 Feb 2020 04:46:31 +0000 (04:46 +0000)
commit992454e0f2df37a296ad8e173d613977b84e8703
treedb2080e7eb9e470b05d1c77f7ff4d1ac4b009ebdtree
parentd062a82f112640436fdb99f21884363557cede9bcommit | diff
fastmodel: Ensure unset vec reg bits are zero/false.

These bits won't be overwritten with values from IRIS, and so we should
make sure they're cleared and don't have old values or junk.

Change-Id: Ib81780ab523f00d6a4d31841d68a3d83924982a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24327
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/fastmodel/iris/thread_context.cc diff | blob | history