genrtlil: fix mux2rtlil generated wire signedness
authorZachary Snow <zach@zachjs.com>
Wed, 23 Dec 2020 00:38:51 +0000 (17:38 -0700)
committerZachary Snow <zach@zachjs.com>
Wed, 23 Dec 2020 00:49:16 +0000 (17:49 -0700)
commit999eec561752706a8ccb085a692684c745415985
treece1bae2021e2cc8744440a67bae40358db3ec59f
parentd15c63effc49e6227e99412afa8a78afb48de0e1
genrtlil: fix mux2rtlil generated wire signedness
frontends/ast/genrtlil.cc
tests/various/port_sign_extend.v