rpc: new frontend.
authorwhitequark <whitequark@whitequark.org>
Thu, 26 Sep 2019 03:57:16 +0000 (03:57 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 30 Sep 2019 15:53:11 +0000 (15:53 +0000)
commit99a7f39084cf4b9cd21e2a1e4f4a842993dfd147
tree805a7ac04968e138c6759e2fa13b2bc560309b11
parent8f2bdff7b9f948141dfb00a337f9c2acec6b118e
rpc: new frontend.

A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
Makefile
frontends/rpc/Makefile.inc [new file with mode: 0644]
frontends/rpc/rpc_frontend.cc [new file with mode: 0644]
tests/rpc/.gitignore [new file with mode: 0644]
tests/rpc/design.v [new file with mode: 0644]
tests/rpc/exec.ys [new file with mode: 0644]
tests/rpc/frontend.py [new file with mode: 0644]
tests/rpc/run-test.sh [new file with mode: 0755]
tests/rpc/unix.ys [new file with mode: 0644]