v3d: honor the write mask on store operations
authorIago Toral Quiroga <itoral@igalia.com>
Wed, 7 Aug 2019 06:20:35 +0000 (08:20 +0200)
committerIago Toral Quiroga <itoral@igalia.com>
Tue, 13 Aug 2019 06:38:19 +0000 (08:38 +0200)
commit99e9809cab8aacb326b35b3bf50c6cd33edab6b8
tree7cf55afcbb1a59cde0ec7ffaae11b5d1ace34d22
parent3d65d2a4883bcf0cdc2eb3a2eeafda1d3c784b9b
v3d: honor the write mask on store operations

v2:
  - Fix incremental update of the const offset when we need to emit a sequence
    with more than one write because of the writemask.
  - Do not move the tmu write emission to a separate helper.

v3:
  - Get the store writemask before the loop, use ffs to get the first component
    to write and clear writemask bits as we process the components (Eric).
  - Simplified the code that figured out the number of components for the TMU
    config based on the number of tmu writes for stores and atomics.

v4:
  - Code clean-ups (Eric).

Fixes:
KHR-GLES31.core.shader_image_load_store.advanced-cast-cs
KHR-GLES31.core.shader_image_load_store.advanced-cast-fs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchBuffers-cs
KHR-GLES31.core.shader_storage_buffer_object.advanced-switchPrograms-cs
KHR-GLES31.core.shader_storage_buffer_object.basic-operations-case1-cs

Reviewed-by: Eric Anholt <eric@anholt.net>
src/broadcom/compiler/nir_to_vir.c