syscall_emul, riscv: add override keyword to RISCV Process class
authorBrandon Potter <brandon.potter@amd.com>
Mon, 15 May 2017 19:03:20 +0000 (14:03 -0500)
committerBrandon Potter <Brandon.Potter@amd.com>
Thu, 18 May 2017 16:34:52 +0000 (16:34 +0000)
commit9aadcc797263fc268fdd9f921ddffa473f56d78a
treead2d9077f43cefb9dc6e8699376e3ca3a672e486
parent679a0e2ef1cc830c0de7e26ae1ff47df4d6e53b8
syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
src/arch/riscv/process.hh