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(parent: 7b07808) | patch
i965: Add chipset limits for Haswell GT1/GT2.
authorKenneth Graunke <kenneth@whitecape.org>
Sat, 13 Aug 2011 01:27:16 +0000 (18:27 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 29 Jan 2013 01:08:28 +0000 (17:08 -0800)
commit9add4e803877f97ad7f6d479d81d537426f09b6f
treebb2139dc30b018c2a50d4eab969f8303c2ee20bbtree
parent7b07808f741ea31831a953aad58749b75a12a108commit | diff
i965: Add chipset limits for Haswell GT1/GT2.

The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.

NOTE: This is a candidate for the 9.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
src/mesa/drivers/dri/i965/brw_context.c diff | blob | history