Improve read_verilog debug output capabilities
authorClifford Wolf <clifford@clifford.at>
Thu, 21 Mar 2019 19:52:29 +0000 (20:52 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 21 Mar 2019 19:52:29 +0000 (20:52 +0100)
commit9b0e7af6d7c84d9b252acbe0fbbf596c75fc1498
tree31593ca32d2af87b8f793a515644e40fdaef488e
parent8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5
Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/verilog/verilog_frontend.cc