projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: a0466e1) | patch
cxxrtl: emit debug information for alias wires.
authorwhitequark <whitequark@whitequark.org>
Mon, 8 Jun 2020 16:22:30 +0000 (16:22 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 8 Jun 2020 17:09:49 +0000 (17:09 +0000)
commit9b39c6f7442a525c8dbfd94f1af65a0b606e648b
tree7751701892c7b408469a4188e0f081e70cf59e8atree
parenta0466e1a969a40a7e90f8bce244eba6cdc1f2c1ccommit | diff
cxxrtl: emit debug information for alias wires.

Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
backends/cxxrtl/cxxrtl_backend.cc diff | blob | history