Added missing support for mem read enable ports to verilog back-end
authorClifford Wolf <clifford@clifford.at>
Thu, 18 Aug 2016 19:47:02 +0000 (21:47 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 18 Aug 2016 19:47:02 +0000 (21:47 +0200)
commit9b8e06bee177f53c34a9dd6dd907a822f21659be
treed7b4eb45238b7c71f5baffc68a685a58aa2646c3
parentb3a01451a54506addf7493d4e3abaa621aa5689c
Added missing support for mem read enable ports to verilog back-end
backends/verilog/verilog_backend.cc