projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 854e7cc) | patch
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 18 Feb 2020 08:11:40 +0000 (09:11 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 18 Feb 2020 08:13:32 +0000 (09:13 +0100)
commit9baa3ad5bba5508473426ae7286ab3d16f9dfb20
tree2c9d80acd05c41650b81c1467e33189be9fe8559tree
parent854e7cc908f346bc43f9b664a53d4583389f4858commit | diff
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
litex/soc/integration/soc.py diff | blob | history
litex/soc/interconnect/csr_bus.py diff | blob | history