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(parent: 21f2f8c) | patch
hdl.ir: don't expose as ports missing domains added via elaboratables.
authorwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 16:39:21 +0000 (16:39 +0000)
commit9c28b61d9f1025c336b5f47ab714495d862c152a
treea10f414b6db76ea85043bc42df455ba11169acb5tree
parent21f2f8c46efeab16207f1818398e9da6232c3117commit | diff
hdl.ir: don't expose as ports missing domains added via elaboratables.

The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
nmigen/hdl/ir.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history